Field
This disclosure relates generally to electronic circuits and more specifically to a circuit to directly interface a static random access memory (SRAM) with a non-volatile memory.
Related Art
Some data processing systems include a volatile memory, such as SRAM, and a type of non-volatile memory. The non-volatile memory may be, for example, a flash memory, or a resistive non-volatile memory such as a resistive random access memory (RRAM) or a magnetic random access memory (MRAM). Volatile memory types lose their stored states when powered down while non-volatile memory types retain their stored states. Because SRAM is faster than most types of memory, normal operations may be carried out using the SRAM and then, when the system is to be powered down, information that is to be retained while the power is off is stored in the non-volatile memory. When power is restored, the data stored in non-volatile memory is reloaded in the SRAM. Thus, normal operations are achieved with the SRAM with the attendant benefits thereof and the non-volatile function is present when power is removed. However, in a data processing system such as a system-on-a-chip (SoC), typically the SRAM and non-volatile memory are each coupled to a system bus using a bus interface circuit. The bus interface circuit may involve using a processor or direct memory access (DMA) controller to access the memory. Anytime a memory is accessed, or when data is transferred between components coupled to the bus, the bus cannot be used by another component of the data processing system while the transfer is taking place. Also, most SRAM cells include at least six transistors and therefore an SRAM array occupies a much larger surface area of an integrated circuit than a correspondingly sized non-volatile memory array.
Therefore, a need exists for a memory system that solves the above problems.